Chiplet (INNOLINK™)

Innosilicon INNOLINK™ IP provides a leading-edge chiplet solution allowing massive amounts of low-latency data to pass seamlessly between smaller chips as if they were all on the same bus. Chiplets, defined as independent functional blocks making up a large chip, are pivotal in this new era of heterogeneous integration to achieve performance and efficiency gains. Based on this, Innosilicon launches the INNOLINK™ chiplet solution as a critical enabler of the power- and cost-efficient die-to-die (D2D), chip-to-chip (C2C), board-to-board (B2B) and package-to-package (P2P) connectivity for data center, networking, 5G, HPC and AI applications.

Innosilicon INNOLINK™ IP is designed to maximize bandwidth between dies / chips / boards / packages, compared to other interfaces available today, at lower power and smaller area budgets. By offering three interconnect options (A/B/C), INNOLINK™ IP can be tailored to customer’s different requirements with an easy-to-use system interface. It is architected for high programmability and flexibility, enabling optimized bandwidth up to over 1.5Tbps while maintaining signal integrity and low latency. Adopting the INNOLINK™ IP in your system will definitely benefit high performance computing ASICs/FPGAs, such as CPU, GPU, AI accelerator, and much more.



  • Meets the performance, efficiency and reliability requirements of B2B/C2C interconnects
  • Delivers up to 56Gbps+/pair
  • Leverages high-speed Long-Reach SerDes technology
  • Low jitter phase-locked loops (PLLs) provide robust timing recovery


  • Meets the performance, efficiency and reliability requirements of C2C/P2P interconnects
  • Delivers up to 16Gbps/pin
  • Utilizes single-ended signal bus with differential clock
  • Extendable with 8-bit data/lane
  • Bidirectional IO with soft-defined input/output
  • Robust clock forwarded architecture


  • Meets the performance, efficiency and reliability requirements of D2D interconnects
  • Delivers up to 24Gbps/pin, 192Gbps/lane, a total of 1.536TB/s for 64 lanes with extremely small number of pins
  • 8 bit per lane with scalability to 2, 4, 8, 16, 32, 64
  • Utilizes single-ended signal bus with differential clock
  • Ultra-low power with 0.5V IO voltage
  • Compatible with advanced 2.5D/3D packaging solutions
  • Optimized for interposer


  • Available in any 40nm or below technology nodes
  • Significantly lower cost, shorter time to market, lower supply risks for OEMs and simpler architectural partitioning than the monolithic silicon integration
  • Offers leading performance, power, and area per terabit
  • Flexible configuration with support for silicon interposer, package substrate and PCB options
  • Customizable synthesis for any FPGAs and ASICs
  • Full support from IP delivery to production


  • High performance computing (HPC) applications
  • Next-generation data center
  • Networking
  • 5G communication
  • Artificial intelligence / machine learning (AI/ML) applications