The Open NAND Flash Interface (ONFI) is an Open standard for NAND Flash Memory chips. The ONFI rev4.2 supports multiple modes of operation like SDR, NV-DDR, NV-DDR2, and NV-DDR3 modes.
Innosilicon ONFI rev4.2 PHY incorporates the full TX/RX logic for NV-DDR, NV-DDR2 and NV-DDR3 modes of operation, and is backwards compatible to SDR mode of operation.
The SDR data interface is the traditional NAND interface that use RE_n to latch data read, WE_n to latch data written, and does not include a clock. The NV-DDR data interface includes a clock that indicates when commands and addresses should be latched, and a data strobe that indicates when data should be latched, supporting transfer rate up to 200MT/s. The NV-DDR2 data interface includes additional capabilities for scaling speed like on-die termination and differential signaling, supporting transfer rate up to 800MT/s. The NV-DDR3 data interface includes all NV-DDR2 features, but operates at VccQ=1.2V, with maximum speed is up to 1600MT/s.
Innosilicon ONFI rev4.2 PHY supports data training, multiple driven strength, and ZQ calibration to achieve highest operation rate while maintaining best signal integration. DLL is integrated inside PHY to provide clock with adjustable phase.
Innosilicon ONFI rev4.2 PHY includes all IOs needed in ONFI interface, with ESD protection circuit included. And it is backward compatible with previous version of ONFI standards. The IO set consists of driver/receiver cells, the ODT/driver impedance calibration cell, and the voltage reference cell to support both single-ended and differential ONFI 4.2 signaling.
The IO library supports all features defined in the ONFI 4.2 specification with low power consumption and area-efficient design.